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Microchip Technology /ATSAML11E16A /CoreDebug /DCRSR

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Interpret as DCRSR

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https://regviz.com/r/Microchip Technology/ATSAML11E14A/CoreDebug/DCRSR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0REGSEL0 (REGWnR)REGWnR

Description

Debug Core Register Select Register

Fields

REGSEL

Register selector
REGWnR

Register write/not-read access

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data